Upcoming Seminar on Using Your Power Supply to Improve Test Throughput

I have provided here on “Watt’s up?” a number of ideas on how you can improve your test throughput from time to time, as it relates on how to make better use of you system power supplies to accomplish this. I have categorized these ideas on how to improve throughput as either fundamental or advanced.

In “How fundamental features of power supplies impact your test throughput” (click here to review) I shared in a two-part posting definitions of key fundamental power supply features that impact test throughput and ways to make improvements to literally shave seconds off of your test time.

One example (of several) of an advanced idea on improving throughput I previously shared here is “Using the power supply status system to improve test throughput” (click here to review). Here I explain how, by monitoring the status system, you can improve throughput by not relying on using excessively long fixed wait statements in your programming.

I hope you have found these ideas helpful. If you would like to learn more about using your system power supply to improve your test throughput I will be presenting a live web-based seminar this week, in just a couple of days, April 30^th, at 1:00 PM EST on this very topic!

In this seminar I will go through a number of things I’ve shared here on “Watt’s up?” in the past, but in greater detail. In addition, I have also prepared several new ideas as well in this seminar that you might find of help for your particular test situation.  You can register online at the following (click here to access seminar description and registration).  In case you miss the live event I expect you will be able to register and listen to seminar afterward as well, as it will be recorded.

So if improving your test throughput is important to you I hope you are able to attend the seminar!

Using Binary Data Transfers to Improve Your Test Throughput

From time to time I have shared here on “Watt’s Up?” a number of different ways the system DC power supply in your test set up impacts your test time, and recommendations on how to make significant improvements in the test throughput. Many of these previous posts are based on the first five of ten hints I’ve put together in a compendium entitled “10 Hints on Improving Throughput with your Power Supply” (click here for hints 1-5).

Oscilloscopes, data acquisition, and a variety of other test equipment are often used to capture and digitize waveforms and store large arrays of data during test, the data is then downloaded to a PC. These data arrays can be quite large, from thousands to millions of measurements. For long-term data logging the data files can be many gigabytes in size. These data files can take considerable time to transfer over an instrument bus, greatly impacting your test time.

Advanced system power supplies incorporating digitizing measurement systems to capture waveform measurements like inrush current are no different. This includes a number of system DC and AC power products we provide. Even though you usually have the choice of transferring data in ASCII format, one thing we recommend is instead transfer data in binary format. Binary data transmission requires fewer bytes reducing transfer time by a factor of two or more.

Further details about using binary mode data transfers can be found in hint 7 of another, earlier compendium we did, entitled “10 hints for using your power supply to decrease test time” (click here to access). Between these two compendiums of hints for improving your test throughput I expect you should be able find a few different ideas that will benefit your particular test situation!

Using the power supply status subsystem to improve your test throughput

Continuing on my throughput theme here, one recommendation is to take advantage of the power supply’s status subsystem. Some power supply operations take notably longer than most to complete than others. Two notable examples:

• Initializing a triggered measurement
• Initializing a triggered output transient or output list event

When developing programs you can include long, fixed wait statements to make certain these operations have completed before proceeding. However, this can easily add many tens of milliseconds or more of unnecessary waiting, increasing overall test time.  A better way is to take advantage of the DC power supply’s status subsystem features that eliminate unnecessary waiting for these operations.

Triggered measurement and output sourcing events can substantially speed up testing by providing actions tightly synchronized with other test activities. But they do have some up-front set up overhead time needed for initializing them. Instead of using a fixed programming delay following an initialization operation it is better to take advantage of the Operation Status Group register in the status subsystem, which is illustrated in Figure 1.

Figure 1: Agilent N6700 series DC power system operation status group

The “WTG meas” bit (#3) or “WTG trans bit (#4) in the condition register can be monitored with a loop in the test program to see when they turn true. At the moment the measurement or output sourcing event is initiated and ready for a trigger the test program will then proceed with its execution without incurring any unnecessary additional waiting. This saves a considerable amount of time as illustrated in Figure 2.

Figure 2: Operation-complete wait time distribution

Instead of waiting for the full worst-case each and every time, the wait is now just the actual time. When repeated over and over for all DUTs being tested, the net result is the average of the actual wait time, which in most cases is just a small fraction of the worst case time! The net result can be many tens of milliseconds test time savings, making an improvement in test throughput.

The first five hints of my compendium “10 Hints for Improving Throughput with your Power Supply” can be viewed here: (click here to access).  For those reading our “Watt’s Up?” blog here are getting the opportunity to preview one of the remaining 5 hints yet to be released!

How fundamental features of power supplies impact your test throughput – Part 2

In part 1 of” How fundamental features of DC power supplies impact your test throughput” (click here to access) I shared definitions of some of the fundamental power supply features that impact test throughput, including:

• Command processing time
• Up-programming response time
• Down-programming response time

Another fundamental DC power supply feature impacting test throughput is its measurement time. There are actually two aspects to a DC power supply’s measurement time as depicted in Figure 1:

• Measurement settling time
• Measurement integration time

Figure 1: DC power supply measurement time

A good indicator of a DC power supply having a high performance measurement system is having programmable measurement integration time, or aperture time, often programmed in power line cycles (PLCs).  One reason for having a programmable integration time is for minimizing any 50 or 60 Hz AC line ripple getting into the DC measurement, by setting the time one or more multiples of a PLC.  Setting the time to 1 PLC provides good ripple rejection with relatively good throughput. When AC line ripple is not an issue the integration time can be set even smaller than 1 PLC, further reducing measurement time. When the DC power supply has a programmable measurement integration time it will no doubt also have a fast-responding measurement system as well, typically just milliseconds, to complement the higher achievable throughput with programmable measurement integration time.

In comparison basic DC power supplies commonly use a 100 millisecond fixed integration time to support AC ripple rejection for both 50 and 60 Hz line frequencies. They also have low bandwidth, slow-responding measurement systems, which can long time to settle after any step change in loading, before a valid measurement can be taken.

We have just introduced our Advanced Power System (APS) DC power supplies. This is a family of high-performance, high power (1 and 2 kW) DC power supplies designed to address the most demanding test challenges. These fundamental throughput-related features for APS are typically more than two orders of magnitude faster compared to more basic-performance DC power supplies, providing much better throughput in manufacturing test. A colleague of mine recently posted details of their introduction on his “General Purpose Electronic Test Equipment (GEPETE)” blog (click here to access) which I believe you will find of interest. Included in this introduction is a link on throughput that takes you to a series of application briefs I have written that go into more detail on improving test throughput with the DC power supply, which you may find very useful.

So how much test throughput improvement might you expect to see by switching from a basic-performance DC source to a high-performance DC source? Well, it really depends on how much the testing makes use of the DC power supply. If it only uses the power supply to provide a fixed DC bias to the device under test (DUT) that never changes for the duration of the test then it will not make a significant difference. More often than not however, a DUT is tested at several bias voltages with several current drain measurements taken for the various bias voltage settings and DUT operating modes. This can add up to a considerable amount of test time. In this case a high-performance DC power supply can more than pay for itself many times over due to improved test throughput.  To get an idea of the kind of difference a high-performance DC power supply can make I set up a representative benchmark test It compares the throughput performance one of our new APS DC power supplies to that of a more basic-performance power supply.  If you are interested in finding out how much difference it made, I made a video of this benchmark testing, entitled “Increasing Test Throughput with Advanced Power System” (click here to access). All I am going to say here is it is an impressive difference but you will need to watch the video to see how much difference!

Establishing Measurement Integration Time for Leakage Currents

The proliferation of mobile wireless devices drives a corresponding demand for components going into these devices. A key attribute of these components is the need to have low levels of leakage current during off and standby mode operation, to extend the battery run-time of the host device. I brought up the importance of making accurate leakage currents quickly in an earlier posting “Pay Attention to the Impact of the Bypass Capacitor on Leakage Current Value and Test Time”(click here to review). Another key aspect about making accurate leakage currents quickly is establishing the proper minimum required measurement integration time. I will go into factors that govern establishing this time here.

Assuming the leakage current being drawn by the DUT, as well as any bypass capacitors on the fixture, have fully stabilized, the key thing with selecting the correct measurement integration time is getting an acceptable level of measurement repeatability. Some experimentation is useful in determining the minimum required amount of time. The primary problem with leakage current measurement is one of AC noise sources present in the test set up. With DC leakage current being just a few micro amps or less these noises are significant. Higher level currents can be usually measured much more quickly as the AC noises are relatively negligible in comparison. There are a variety of potential noise sources, including radiated and conducted from external sources, including the AC line, and internal noise sources, such as the AC ripple voltage from the DC source’s output. This is illustrated in Figure 1 below. Noise currents directly add to the DC leakage current while noise voltages become corresponding noise currents related by the DUT and test fixture load impedance.

Figure 1: Some noise sources affecting DUT current measurement time

Using a longer measurement time integrates out the peak-to-peak random deviations in the DC leakage current to provide a consistently more repeatable DC measurement result, but at the expense of increasing overall device test time. Measurement repeatability should be based on a statistical confidence level, which I will do into more detail further on. Using a measurement integration time of exactly one power line cycle (1 PLC) of 20 milliseconds (for 50 Hz) or 16.7 milliseconds (for 60 Hz) cancels out AC line frequency noises. Many times a default time of 100 milliseconds is used as it is an integer multiple of both 20 and 16.7 milliseconds. This is fine if overall DUT test time is relatively long but generally not acceptable when total test time is just a couple of seconds, as is the case with most components. As a minimum, setting the measurement integration time to 1 PLC is usually the prudent thing to do when short overall DUT test time is paramount.

Reducing leakage current test time below 1 PLC means reducing any AC line frequency noises to a sufficiently low level such that they are relatively negligible compared to higher frequency noises, like possibly the DC source’s wideband output ripple noise voltage and current. Proper grounding, shielding, and cancellation techniques can greatly reduce noise pickup. Paying attention to the choice and size of bypass capacitors used on the test fixture is also important. A larger-than-necessary bypass capacitor can increase measured noise current when the measuring is taking place before the capacitor, which is many times the case. Establishing the requirement minimum integration time is done by setting a setting an acceptable statistical confidence level and then running a trial with a large number of measurements plotted in a histogram to assure that they fall within this confidence level for a given measurement integration time. If they did not then the measurement integration time would need to be increased. As an example I ran a series of trials to determine what the acceptable minimum required integration time was for achieving 10% repeatability with 95% confidence for a 2 micro amp leakage current. AC line noises were relatively negligible. As shown in Figure 2, when a large series of measurements were taken and plotted in a histogram, 95% of the values fell within +/- 9.5% of the mean for a measurement integration time of 1.06 milliseconds.

Figure 2: 2 Leakage current measurement repeatability histogram example

Leakage current measurements by nature take longer to measure due to their extremely low levels. Careful attention to minimizing noise and establishing the minimum required measurement integration time contributes toward improving the test throughput of components that take just seconds to test.

Pay Attention to the Impact of the Bypass Capacitor on Leakage Current Value and Test Time

It is no secret there is big demand for all kinds of wireless battery powered devices and, likewise, the components that go into these devices. These devices and their components need to be very efficient in order to get the most operating and standby time out of the limited amount of power they have available from the battery. Off-mode and leakage currents of these devices and components need to be kept to a minimum as an important part of maximizing battery run and standby time. Levels are typically in the range of tens of microamps for devices and just a microamp or less for a component. Off-mode and leakage currents are routinely tested in production to assure they meet specified requirements. The markets for wireless battery powered devices and their components are intensely competitive. Test times need to be kept to a minimum, especially for the components. It turns out the choice of the input power bypass capacitor being used, either within the DUT on the DUT’s test fixture, can have a large impact on the leakage current value and especially the test time for making an accurate leakage current measurement.

Good things come in small packages?
A lot has been done to provide greater capacitance in smaller packages for ceramic and electrolytic capacitors, for use in bypass applications. It is worth noting that electrolytic and ceramic capacitors exhibit appreciable dielectric absorption, or DA. This is a non-linear behavior causing the capacitor to have a large time-dependent charge or discharge factor, when a voltage or short is applied. It is usually modeled as a number of different value series R-C pairs connected in parallel with the main capacitor. This causes the capacitor to take considerable time to reach its final steady state near-zero current when a voltage is applied or changed. When trying to test the true leakage current on a DUT it may be necessary to wait until the current on any bypass capacitors has reached steady state before a current measurement is taken. Depending on the test time and capacitor being used this could result in an unacceptably long wait time.

So how do they compare?
In Figure 1 I captured the time-dependent current response waveform for a 5.1 megohm resistor, a 5.1 megohm resistor in parallel with 100 microfarad electrolytic capacitor, and finally a 5.1 megohm resistor in parallel with 100 microfarad film capacitor, when a 5 volt step stimulus was applied.

Figure 1: Current response of different R-C loads to 5 volt step

The 5.1 megohm resistor (i.e. “no capacitor”) serves as a base line to compare the affect the two different bypass capacitors have on leakage current measurement. The film capacitor has relatively ideal electrical characteristics in comparison to an equivalent electrolytic or ceramic capacitor. It settles down to near steady state conditions within 0.5 to 1 second. At 3 to 3.5 seconds out (marker placement in Figure 1) the film capacitor is contributing a fairly negligible 42 nanoamps of additional leakage. In comparison the electrolytic capacitor current is still four times as great as the resistor current and nowhere near being settled out. If you ever wondered why audio equipment producers insist on high performance film capacitors in critical applications, DA is one of those reasons!

So how long did it take for the electrolytic capacitor to reach steady state? I set up a longer term capture in Figure 2 for the electrolytic capacitor. After about a whopping 40 seconds later it seemed to be fully settled out, but still contributing a substantial 893 nanoamps of additional steady state leakage current.

Figure 2: 100 microfarad electrolytic capacitor settling time

Where do I go from here?
So what should one do when needing to test leakage current? When testing a wireless device be aware of what kind and value of bypass capacitor has been incorporated into it. Most likely it is a ceramic capacitor nowadays. Film capacitors are too large and cost prohibitive here. Find out how long it takes to settle to its steady state value. Also, off-state current measurements are generally left until the end of the testing to not waste time waiting for the capacitor to reach steady state. If testing a component, if a bypass capacitor is being used on the test fixture, consider using a film capacitor. With test times of just seconds and microamp level leakage currents the wrong bypass capacitor can be a huge problem!